Carbon nanotubes, which can be either semiconducting or metallic, are typically grown by arc discharge, laser ablation, or chemical vapor deposition. The nanotubes are then harvested from the growth surface for subsequent use [H. Dai, Acc. Chem. Res. 35, 1035 (2002)]. Once harvested, one remaining challenge is to position the carbon nanomaterials for use in devices, e.g., positioning them between electrodes on selected substrates for electronic, optoelectronic or sensing applications. At the research level, individual carbon nanotubes are commonly brought into contact with electrodes by one of two techniques. In one instance, the carbon nanotubes can be deposited onto surfaces patterned with electrodes by spin-coating from a dispersion. However, only a small portion of the individual nanotubes actually come in contact with the electrodes. A second technique involves spin-coating the carbon nanotubes on a surface prior to electrode deposition. The electrodes are subsequently deposited with or without alignment of the electrodes to the carbon nanotubes. The successful formation of electrical devices using carbon nanotubes is limited by serendipitous electrode patterning or random nanotube deposition or if the electrodes are intentionally aligned to the nanotubes, to small numbers of devices.
At the research level the attractive performance of carbon nanotubes in electronics and optoelectronics has been demonstrated, however, challenges remain with regard to scale-up of carbon nanotube device application and, in particular, in providing reliable contacts between the nanotubes and the electrodes of the device. Routes that form carbon nanotubes in selected areas of a substrate avoiding exposure of the nanotubes to the potentially harmful solvents and oxidation processes used in harvesting, purification, and placement have recently been shown to form better performing devices. [J. Liu, S. Fan, H. Dai, MRS Bull. April, 244 (2004)].
Semiconductor nanowires are also typically grown by chemical vapor deposition and harvested from the growth surface for further use. A semiconductor nanowire is a one-dimensional semiconductor. The semiconductor materials can be Group IV (such as Si, Ge, or an alloy), Group III-V (such as GaAs), Group II-VI (such as CdSe, CdS, ZnS), Group IV-VI (such as PbSe) Thus, they face many of the same challenges in alignment and placement as carbon nanotubes for device applications [C. M. Lieber, MRS Bull. July, 286 (2003)]. Again, the process of harvesting and positioning nanowires on surfaces subjects the nanostructures to potentially harmful conditions. Methods for in-place growth of nanowires are therefore preferred. [J. Li, C. Lu, B. Maynor, S. Huang, J. Liu, Chem. Mat. 16, 1633 (2004)].
Microfluidics has been used to orient and selectively deposit nanowires and nanotubes on surfaces, but microfluidic channels are typically limited to micron widths by the fluidics of liquid flow at small dimensions [H. Yuang, X. Duan, Q. Wei. C. Lieber, Science 291, 630 (2001)]. Microfluidic approaches also would require the use of surfactants to disperse the nanowires and nanotubes in the delivery solutions. The presence of surfactants, particularly for nanotube deposition, can significantly affect the electronic properties of the nanotubes or nanowires unless the surfactants can be removed from the resulting nanomaterials. This approach requires the separate growth, harvesting, and placement of nanowires and nanotubes.
Ordered networks of suspended carbon nanotubes have been grown between regularly positioned silicon posts by patterning the catalysts on the posts and growing the nanotubes until they reach another post. [N. Franklin, H. Dai, Adv. Mat. 12, 890 (2000)]. In addition electric fields have been used to control the direction of nanotube growth by taking advantage of their high polarizability [H. Dai, Acc. Chem. Res. 35, 1035 (2002)]. In both instances, the nanotubes are suspended above the substrate surface. For many electronic and optoelectronic device applications, the nanotube is preferably in contact with the substrate surface, e.g., the gate dielectric of a transistor for conductance modulation.
Carbon nanotubes and semiconductor nanowires have been formed as vertical arrays on surfaces by spatially positioning catalytic sites. This approach typically provides a high density of at least locally ordered nanotubes and nanowires that extend perpendicular to the substrate surface. Although this approach may eliminate the need to harvest and place the nanotubes or nanowires in some applications, vertical arrays of these materials place severe constraints on device geometries and assumes that the growth surface is amenable to the desired device structure.
To position the catalysts for nanotube or nanowire growth on surfaces, lithographic processing is commonly used. The catalysts used are either metal containing organic molecules or nanoparticles of metal or metal oxide [For examples see J. Liu, S. Fan, H. Dai, MRS Bulletin, April, 244 (2004); S. Rosenblatt et. al., Nano Lett. 2, 869 (2002); and J. Hu, T. W. Odom, C. M. Lieber, Acc. Chem. Res. 32, 435 (1999)]. Lithographic patterning of surfaces is useful across the substrate plane, but does not provide a route to pattern surfaces vertically.